Development of a prototype module for a DEPFET pixel vertex detector for a linear collider

For operation at a linear collider the excellent noise performance of depleted field effect transistor (DEPFET) pixels allows building very thin detectors with high spatial resolution and low power consumption. However, high readout speeds of 50 MHz line rate and 20 kHz for the full detector must be reached. A prototype system is presented, using a new DEPFET pixel matrix (128 /spl times/ 64 pixels), fast steering chips (Switcher II) for row wise operation and a fast current based readout chip (CURO II). The sensors with small linear DEPFET pixels (22/spl times/36 /spl mu/m/sup 2/) are optimized for fast readout and high spatial resolution. Measurements show that the complete removal of the accumulated signal charge from the internal gate (complete clear), which is fundamental for the foreseen readout mode, is feasible. The current based readout chip CUROII, containing current memory cells, pedestal subtraction and on chip zero suppression for a triggerless operation has been fabricated and tested. First results of a full prototype system are presented.