Effect of silicon thickness on the degradation mechanisms of sequential laterally solidified polycrystalline silicon TFTs during hot-carrier stress

We have investigated bias stress-induced aging effects in polycrystalline silicon thin-film transistors (poly-Si TFTs), as a function of the active layer thickness. Two aging mechanisms were identified: hot-carrier injection in the gate insulator and deep-state generation in the active "body." Hot-carrier injection was found dominant in devices having very thin (30 nm) or thick (100 nm) active layers. Deep-state generation dominated in devices having intermediate active layer thickness (50 nm). The fully depleted aspect of ultrathin active-layer devices, as well as their relative immunity to substantial degradation under bias stress, favor the implementation of thin active layer for the fabrication of high-performance and high-reliability poly-Si TFTs.