A 0.027-mm super(2) Self-Calibrating Successive Approximation ADC Core in 0.18-[mu]m CMOS

We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-[mu]m CMOS process and consumes 118[mu]W at 1.8V power supply. Also, the active area of ADC core is realized to be 0.027mm super(2). The calibration improves the SNDR by 13.4dB and the SFDR by 21.0dB. The measured SNDR and SFDR at 1kHz input are 55.2dB and 73.2dB respectively.