An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference

This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area an...

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Veröffentlicht in:IEICE Transactions on Electronics 2011/06/01, Vol.E94.C(6), pp.960-967
Hauptverfasser: Indika U. K. BOGODA APPUHAMYLAGE, OKURA, Shunsuke, IDO, Toru, TANIGUCHI, Kenji
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Sprache:eng
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Zusammenfassung:This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18µm CMOS process, and simulation results are presented. With a 1.6V supply, the reference produces an output of about 628.5mV, and simulated results show that the temperature coefficient of output is less than 13.8ppm/°C in the temperature range from 0°C to 100°C. The average current consumption is about 8.5µA in the above temperature range. The core circuit, including current source, opamp, current mirrors and switched capacitor filters, occupies less than 0.0064mm2 (80µm × 80µm).
ISSN:0916-8524
1745-1353
1745-1353
DOI:10.1587/transele.E94.C.960