Design for Testability That Reduces Linearity Testing Time of SAR ADCs

Design for Testability That Reduces Linearity Testing Time of SAR ADCs

This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since th...

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Veröffentlicht in:IEICE Transactions on Electronics 2011/06/01, Vol.E94.C(6), pp.1061-1064
Hauptverfasser: OGAWA, Tomohiko, KOBAYASHI, Haruo, UEMORI, Satoshi, TAN, Yohei, ITO, Satoshi, TAKAI, Nobukazu, YAMAGUCHI, Takahiro J., NIITSU, Kiichi
Format: Artikel
Sprache:eng
Schlagworte:
built-in self-test
Circuits
Cost engineering
DC linearity
design for testability
Direct current
Electronics
Linearity
SAR ADC
Synthetic aperture radar
Testability
testing
Testing time
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Beschreibung
Zusammenfassung:This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.
ISSN:0916-8524
1745-1353
1745-1353
DOI:10.1587/transele.E94.C.1061