A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM

We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, to achieve an expanded “read” and “write” margins and low leakage power in a 90-nm, 2-kbit, six-transistor CMOS SRAM. At the threshold voltage fluctuation of 6σ, the minimum supply voltage of the newly developed (dvlp.) SRAM for “write” operation was significantly reduced to 0.11V, less than half that of an equivalent conventional (conv.) SRAM. The standby leakage power of the dvlp. SRAM was only 1.17µW, which is 4.64% of that of the conv. SRAM at supply voltage of 1.0V. Moreover, the maximum operating clock frequency of the dvlp. SRAM was 138MHz, which is 15% higher than that (120MHz) of the conv. SRAM at VMM of 0.4V. An area overhead was 0.81% that of the conv. SRAM.