Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

Sub-10-nm planar bulk CMOS devices were demonstrated by a lateral source/drain (S/D) junction control, which consists of the notched gate electrode, shallow S/D extensions, and steep halo in a reverse-order S/D formation. Furthermore, the transport properties were also evaluated by using those sub-10-nm planar bulk MOSFETs. The direct-tunneling currents between the S/D regions, with not only the gate length but also the "drain-induced tunneling modulation (DITM)" effects, are clearly observed for the sub-10-nm CMOS devices at low temperature. Moreover, a quantum mechanical simulation reveals that the tunneling currents increase with the increase in the temperatures and gate voltages, resulting in a certain amount of contribution to the subthreshold current even at 300 K. Therefore, it is strongly required that the supply voltage should be reduced to suppress the DITM effects for the sub-10-nm CMOS devices even under the room-temperature operations