A 5-GHz Mesh Interconnect for a Teraflops Processor

A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores....

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Veröffentlicht in:	IEEE MICRO 2007-09, Vol.27 (5), p.51-61
Hauptverfasser:	Hoskote, Y., Vangal, S., Singh, A., Borkar, N., Borkar, S.
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth Bandwidths CMOS digital integrated circuits crossbar Delay Engines Intelligent networks Interconnect Interconnection interconnection fabric mesh Microprocessors Multiprocessor interconnection networks Nanocomposites Nanomaterials Nanostructure network on chip Network topologies Network-on-a-chip Networks Power dissipation router Scalability Two dimensional
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Beschreibung
Zusammenfassung:	A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.
ISSN:	0272-1732 1937-4143
DOI:	10.1109/MM.2007.4378783