Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of In sub(0.52)Al sub(0.48)As/In sub( 0.53)Ga sub(0.47)As p-HEMTs

The characteristics of 0.15- mum InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In sub(0.52)Al sub(0.48)As barrier and showed a much higher etch selectivity (~70) of the InP spacer against the In sub(0.52)Al sub(0.48)As barrier. The 0.15-mum InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G sub(m,max) (1.38 S/mm), I sub(ON)n/I sub(OFF)(1.18X10 super(4)), drain-induced barrier lowering (80 mWV), threshold voltage uniformity (V sub(th,avg) = -190 mV and alpha = 15 mV), and ftau (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area.