A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification

A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification

This paper presents a compositional method with failure-preserving abstraction for scalable asynchronous design verification. It combines efficient state-space reductions and novel interface refinement and can dramatically reduce the complexity of state space while decreasing the introduction of fal...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 2008-07, Vol.27 (7), p.1343-1347
Hauptverfasser: Hao Zheng, Ahrens, J., Tian Xia
Format: Artikel
Sprache:eng
Schlagworte:
Abstraction
asynchronous
Complexity
compositional
Computer aided design
Computer science
Design engineering
Design methodology
Engineering profession
Explosions
Failure
Formal verification
Integrated circuits
Machine learning
Minimization methods
model checking
Productivity
Reduction
refine
State-space methods
System testing
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper presents a compositional method with failure-preserving abstraction for scalable asynchronous design verification. It combines efficient state-space reductions and novel interface refinement and can dramatically reduce the complexity of state space while decreasing the introduction of false failures. This allows much larger designs to be verified as demonstrated in the experimental results.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2008.923104