A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhbox m LTPS-TFT Technology

A phase-locked loop (PLL) with self-calibrated charge pumps (CPs) has been fabricated in a 3-mum low-temperature polysilicon thin-film transistor (LTPS-TFT) technology. A voltage scaler and self-calibrated CPs are used to reduce the static phase error, reference spur, and jitter of an LTPS-TFT PLL. This PLL operates from 5.6 to 10.5 MHz at a supply of 8.4 V. Its area is 18.9 mm super(2), and it consumes 7.81 mW at 10.5 MHz. The measured static phase error without and with calibration is 80 and 6.56 ns, respectively, at 10.5 MHz. The measured peak-to-peak jitter without and with calibration is 3.573 and 2.834 ns, respectively. The measured reference spur is -26.04 and -30.2 dBc without and with calibration, respectively. The measured maximal locked time is 1.75 ms.