Stress Memorization TechniqueaFundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

Stress Memorization TechniqueaFundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies...

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Veröffentlicht in:IEEE transactions on electron devices 2009-01, Vol.56 (8)
Hauptverfasser: Ortolland, C, Okuno, Y, Verheyen, P, Kerner, C, Stapelmann, C, Aoulaiche, M, Horiguchi, N, Hoffmann, T
Format: Artikel
Sprache:eng
Schlagworte:
CMOS
Devices
Gates
Intermetallics
Silicides
Stresses
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Beschreibung
Zusammenfassung:In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.
ISSN:0018-9383
DOI:10.1109/TED.2009.2024021