Demonstration of 60-GHz Link Using a 1.6-Gb/s Mixed-Mode BPSK Demodulator

A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18-µm CMOS process. The proposed demodulator scheme does not require any analog-to-digital converters (ADC) and, consequently, can have...

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Veröffentlicht in:	IEICE Transactions on Electronics 2010/12/01, Vol.E93.C(12), pp.1704-1707
Hauptverfasser:	CHOI, Kwang-Chun, KO, Minsu, KIM, Duho, CHOI, Woo-Young
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences binary phase shift keying BPSK Chip formation Chips Circuit properties CMOS Demodulation demodulator Demodulators Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology High speed IEEE802.15.3c Integrated circuits Integrated circuits by function (including memories and processors) Links modem Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors Wireless communication wireless PAN
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Zusammenfassung:	A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18-µm CMOS process. The proposed demodulator scheme does not require any analog-to-digital converters (ADC) and, consequently, can have advantages over the conventional schemes for high-data-rate demodulation. The demodulator core consumes 53.8mW from 2.5-V power supply while the chip area is 380×500µm2. The fabricated chip is verified by 60-GHz wireless link tests with 1.6-Gb/s data.
ISSN:	0916-8524 1745-1353
DOI:	10.1587/transele.E93.C.1704