Area reduction techniques for full integrated distributed amplifier

This paper presents two techniques to reduce the area in the design of CMOS distributed amplifiers. The proposed techniques take into account the influence of compacting the layout and the use of stacked inductor for the artificial transmission lines on the distributed amplifier performance. Following these design guidelines, three prototypes have been fabricated in a low cost CMOS 0.35 μ m process. The measured gain is about 6 dB with a cutoff frequency around 8 GHz. The noise figure varies from 5 to 7 dB and the circuits draw 30 mA from a 3.3 V voltage supply. With the developed area optimization design techniques, a maximum area reduction of 37% with respect to a conventional design has been achieved, without any significant performance degradation.