Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit

A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490MHz and a supply voltage (VDD) of 0.75V was 104.1µW, i.e., 21.6% that (482.3µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51nW, which was only 1.69% that (1, 153nW) of the conventional SR circuit.