The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance o...

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Veröffentlicht in:IEICE Transactions on Electronics 2009/03/01, Vol.E92.C(3), pp.352-355
Hauptverfasser: JUNG, Ki-Sang, KIM, Kang-Jik, KIM, Young-Eun, CHUNG, Jin-Gyun, PYUN, Ki-Hyun, LEE, Jong-Yeol, JEONG, Hang-Geun, CHO, Seong-Ik
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Sprache:eng
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