A Design of the Signal Processing Hardware Platform for Communication Systems

In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900K gates, two DSPs with maximum 8,000 MIPS at 1GHz clock, 2-channel ADC and DAC supporting maximum 125MHz sampling ra...

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Veröffentlicht in:IEICE Transactions on Communications 2008/03/01, Vol.E91.B(3), pp.939-942
Hauptverfasser: LEE, Byung Wook, CHO, Sung Ho
Format: Artikel
Sprache:eng
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