Bitonic sorting using an optoelectronic recirculating architecture

An optoelectronic bitonic sorter based on a recirculating architecture is presented. The data are input inword parallel-bit parallel fashion and processed by two smart pixel arrays made up of bitwise compare-and-exchange modules. Along with the logic design, the control and synchronization of the bitwise compare-and-exchange modules are discussed. Finally, the capacity, hardware requirements, response time, and throughput of the recirculating bitonic sorter are compared with a pipeline implementation. The proposed recirculating architecture is shown to require less hardware than the pipelined systems. However, the decrease in hardware results in a decrease in system throughput.