Effect of surface characteristic on room-temperature silicon direct bonding

Silicon direct bonding plays an important role in micro/nano-fabrication and integration. However, silicon surface when not in good condition will result in voids or gaps in the bonding interface or even a complete failure to bond. In this paper the effect of surface characteristic on room-temperature silicon direct bonding is investigated. It is found that the occurrence of bonding is related to surface energy, micro/nano-topography and elasticity of silicon wafers. Then a dimensionless parameter, α, is presented in detail, and two critical values, 0.570 and 1.065 are obtained: when α > 1.065, indicating that the normalized combined force of both adhesion force and external force F ˆ ≤ 0 and d F ˆ / d c ≤ 0 , the bonding wave will spread quickly and spontaneous bonding will occur; when 1.065 > α > 0.57, F ˆ ≤ 0 and it will facilitate silicon direct bonding but not guaranteeing bonding spontaneously; when α < 0.57, F ˆ > 0 , the bonding resistance needs to be overcome for silicon bonding. If α is very close to 0.57 and enough external pressure is provided, silicon wafer pairs will bond slowly and voids or gaps may exist in the interface, otherwise they will fail to bond. Experiments of silicon direct bonding with wafers in different surface characteristics were used to verify the model. The analysis results prove that the model describes the experiments very well. Thus, the model provides a general route for assessing the impact of surface characteristic in direct bonding, and can be employed when evaluating different processes for silicon direct bonding applications.