Double-fin FETs based on standard CMOS approach

Double-fin FETs based on standard CMOS approach

Double-fin p-MOSFETs have been fabricated using PaDEOx process. SOI 133 nm wide and bulk 260 nm-wide FinFETs have been electrically characterized and compared with the photolithographically patterned 9 μm wide fin transistor based on the same layout. Extraction of device parameters: g M , V T , SS,...

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Veröffentlicht in:Microelectronic engineering 2010-05, Vol.87 (5), p.1396-1399
Hauptverfasser: Zaborowski, Michał, Tomaszewski, Daniel, Panas, Andrzej, Grabiec, Piotr
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
CMOS
Design. Technologies. Operation analysis. Testing
Devices
Electronics
Exact sciences and technology
Extraction
FinFETs
Glass transition temperature
Integrated circuits
Microelectronic fabrication (materials and surfaces technology)
Microelectronics
Nanoengineering
PaDEOx
Photolithography
Semiconductor devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Si nanolines
Transistors
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Beschreibung
Zusammenfassung:Double-fin p-MOSFETs have been fabricated using PaDEOx process. SOI 133 nm wide and bulk 260 nm-wide FinFETs have been electrically characterized and compared with the photolithographically patterned 9 μm wide fin transistor based on the same layout. Extraction of device parameters: g M , V T , SS, I D , off , R s , R c has been done using sets of devices of different dimensions. The characterization results confirm advantages of double-fin devices.
ISSN:0167-9317
1873-5568
DOI:10.1016/j.mee.2009.11.162