Instruction Set Innovations for the Convey HC-1 Computer

The Convey HC-1 is a heterogeneous computing system based on an industry-standard Intel processor and a proprietary coprocessor that share virtual memory and an instruction stream, creating a hybrid-core computing system. The coprocessor architecture supports user-defined, dynamically loadable instr...

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Veröffentlicht in:	IEEE MICRO 2010-03, Vol.30 (2), p.70-79
1. Verfasser:	Brewer, Tony M
Format:	Artikel
Sprache:	eng
Schlagworte:	Acceleration accelerators Application software Computation Computer aided instruction Computer architecture Computer memory Computer science Conveying Coprocessors Decoding Dynamical systems Dynamics Field programmable gate arrays FPGAs heterogeneous computing hybrid-core computing instruction set design Instruction sets (computers) Logic programming Microprocessors Multiprocessing Parallel processing Programmable logic arrays reconfigurable computing Systems design Technological innovation
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