Instruction Set Innovations for the Convey HC-1 Computer

Instruction Set Innovations for the Convey HC-1 Computer

The Convey HC-1 is a heterogeneous computing system based on an industry-standard Intel processor and a proprietary coprocessor that share virtual memory and an instruction stream, creating a hybrid-core computing system. The coprocessor architecture supports user-defined, dynamically loadable instr...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE MICRO 2010-03, Vol.30 (2), p.70-79
1. Verfasser: Brewer, Tony M
Format: Artikel
Sprache:eng
Schlagworte:
Acceleration
accelerators
Application software
Computation
Computer aided instruction
Computer architecture
Computer memory
Computer science
Conveying
Coprocessors
Decoding
Dynamical systems
Dynamics
Field programmable gate arrays
FPGAs
heterogeneous computing
hybrid-core computing
instruction set design
Instruction sets (computers)
Logic programming
Microprocessors
Multiprocessing
Parallel processing
Programmable logic arrays
reconfigurable computing
Systems design
Technological innovation
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The Convey HC-1 is a heterogeneous computing system based on an industry-standard Intel processor and a proprietary coprocessor that share virtual memory and an instruction stream, creating a hybrid-core computing system. The coprocessor architecture supports user-defined, dynamically loadable instruction sets. Managing the decoding, dispatch, and execution of completely user-defined instructions requires an innovative approach to system design and operation.
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2010.36