Evaluation and Analysis of Packet-Length Effect on Networks-on-Chip
The network-on-chip (NoC) design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency,...
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Veröffentlicht in: | Tsinghua science and technology 2010-06, Vol.15 (3), p.288-293 |
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Format: | Artikel |
Sprache: | eng |
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Online-Zugang: | Volltext |
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Zusammenfassung: | The network-on-chip (NoC) design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency, and energy consumption. The appropriate NoC packet-length was selected based on simulation and analysis of the packet-length effect on NoC for variable average data block length (ADBL) configuration parameters. A trade-off curve among throughput, latency, and energy consumption was developed and shows that the optimum packet length increases as the ADBL increases. |
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ISSN: | 1007-0214 1878-7606 1007-0214 |
DOI: | 10.1016/S1007-0214(10)70063-8 |