Procedures based on simulation and hardware for a computer architecture course
In this study, a procedure planning for a Computer Architecture Course that tries to create a balance between simulation and laboratory procedures is presented. For this planning, we use hardware implementation for parts of this subject that require careful dedication because of its complexity: inte...
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| Veröffentlicht in: | Computer applications in engineering education 2002, Vol.10 (1), p.11-17 |
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| container_title | Computer applications in engineering education |
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| creator | González, E. J. Alayón, S. Piñeiro, J. D. Sánchez, J. L. Estévez, J. I. Sigut, J. F. Moreno, L. |
| description | In this study, a procedure planning for a Computer Architecture Course that tries to create a balance between simulation and laboratory procedures is presented. For this planning, we use hardware implementation for parts of this subject that require careful dedication because of its complexity: interconnection networks and parallel processing. On the other hand, we use simulation packages for the teaching of pipelined and vectorial processors. © 2002 Wiley Periodicals, Inc. Comput Appl Eng Educ 10: 11–17, 2002; Published online in Wiley InterScience (www.interscience.wiley.com.); DOI 10.1002/cae.10012 |
| doi_str_mv | 10.1002/cae.10012 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_753650667</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>753650667</sourcerecordid><originalsourceid>FETCH-LOGICAL-c3282-46a8be2e3dd9b53926298fe11d74f51a6e44a7f01073c184537363991b08a6093</originalsourceid><addsrcrecordid>eNp9kD1PwzAQhi0EEqUw8A8ygRhC_RU7HquqLaCqdAA6Wo5zUQNpU-xEpf8elwAbTPfo9Lyn04vQJcG3BGM6sAYOQOgR6hGsVIwTTo8PLEjMpGSn6Mz7V4yxEkz10Hzhagt568BHmfGQR_Um8uW6rUxTBjSbPFoZl--Mg6ioXWQiW6-3bQMBnV2VDdgmpMO2dR7O0UlhKg8X37OPnifjp9FdPHuc3o-Gs9gymtKYC5NmQIHlucoSpqigKi2AkFzyIiFGAOdGFphgySxJecIkC-8qkuHUCKxYH113d7eufm_BN3pdegtVZTZQt17LhIkECyGDefWvSaVgqWA8iDedaF3tvYNCb125Nm6vCdaHbnXoVn91G9xB5-7KCvZ_i3o0HP8k4i5R-gY-fhPGvenwpEz0cj7VDzP-siDLiRbsE9x0iJw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>27638634</pqid></control><display><type>article</type><title>Procedures based on simulation and hardware for a computer architecture course</title><source>Wiley Journals</source><creator>González, E. J. ; Alayón, S. ; Piñeiro, J. D. ; Sánchez, J. L. ; Estévez, J. I. ; Sigut, J. F. ; Moreno, L.</creator><creatorcontrib>González, E. J. ; Alayón, S. ; Piñeiro, J. D. ; Sánchez, J. L. ; Estévez, J. I. ; Sigut, J. F. ; Moreno, L.</creatorcontrib><description>In this study, a procedure planning for a Computer Architecture Course that tries to create a balance between simulation and laboratory procedures is presented. For this planning, we use hardware implementation for parts of this subject that require careful dedication because of its complexity: interconnection networks and parallel processing. On the other hand, we use simulation packages for the teaching of pipelined and vectorial processors. © 2002 Wiley Periodicals, Inc. Comput Appl Eng Educ 10: 11–17, 2002; Published online in Wiley InterScience (www.interscience.wiley.com.); DOI 10.1002/cae.10012</description><identifier>ISSN: 1061-3773</identifier><identifier>EISSN: 1099-0542</identifier><identifier>DOI: 10.1002/cae.10012</identifier><language>eng</language><publisher>New York: Wiley Subscription Services, Inc., A Wiley Company</publisher><subject>Architecture ; Computer simulation ; Education ; Hardware ; Interconnection ; Mathematical models ; networks ; Packages ; procedures ; Processors ; simulation</subject><ispartof>Computer applications in engineering education, 2002, Vol.10 (1), p.11-17</ispartof><rights>Copyright © 2002 Wiley Periodicals, Inc.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c3282-46a8be2e3dd9b53926298fe11d74f51a6e44a7f01073c184537363991b08a6093</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.1002%2Fcae.10012$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://onlinelibrary.wiley.com/doi/full/10.1002%2Fcae.10012$$EHTML$$P50$$Gwiley$$H</linktohtml><link.rule.ids>314,780,784,1417,4024,27923,27924,27925,45574,45575</link.rule.ids></links><search><creatorcontrib>González, E. J.</creatorcontrib><creatorcontrib>Alayón, S.</creatorcontrib><creatorcontrib>Piñeiro, J. D.</creatorcontrib><creatorcontrib>Sánchez, J. L.</creatorcontrib><creatorcontrib>Estévez, J. I.</creatorcontrib><creatorcontrib>Sigut, J. F.</creatorcontrib><creatorcontrib>Moreno, L.</creatorcontrib><title>Procedures based on simulation and hardware for a computer architecture course</title><title>Computer applications in engineering education</title><addtitle>Comput. Appl. Eng. Educ</addtitle><description>In this study, a procedure planning for a Computer Architecture Course that tries to create a balance between simulation and laboratory procedures is presented. For this planning, we use hardware implementation for parts of this subject that require careful dedication because of its complexity: interconnection networks and parallel processing. On the other hand, we use simulation packages for the teaching of pipelined and vectorial processors. © 2002 Wiley Periodicals, Inc. Comput Appl Eng Educ 10: 11–17, 2002; Published online in Wiley InterScience (www.interscience.wiley.com.); DOI 10.1002/cae.10012</description><subject>Architecture</subject><subject>Computer simulation</subject><subject>Education</subject><subject>Hardware</subject><subject>Interconnection</subject><subject>Mathematical models</subject><subject>networks</subject><subject>Packages</subject><subject>procedures</subject><subject>Processors</subject><subject>simulation</subject><issn>1061-3773</issn><issn>1099-0542</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><recordid>eNp9kD1PwzAQhi0EEqUw8A8ygRhC_RU7HquqLaCqdAA6Wo5zUQNpU-xEpf8elwAbTPfo9Lyn04vQJcG3BGM6sAYOQOgR6hGsVIwTTo8PLEjMpGSn6Mz7V4yxEkz10Hzhagt568BHmfGQR_Um8uW6rUxTBjSbPFoZl--Mg6ioXWQiW6-3bQMBnV2VDdgmpMO2dR7O0UlhKg8X37OPnifjp9FdPHuc3o-Gs9gymtKYC5NmQIHlucoSpqigKi2AkFzyIiFGAOdGFphgySxJecIkC-8qkuHUCKxYH113d7eufm_BN3pdegtVZTZQt17LhIkECyGDefWvSaVgqWA8iDedaF3tvYNCb125Nm6vCdaHbnXoVn91G9xB5-7KCvZ_i3o0HP8k4i5R-gY-fhPGvenwpEz0cj7VDzP-siDLiRbsE9x0iJw</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>González, E. J.</creator><creator>Alayón, S.</creator><creator>Piñeiro, J. D.</creator><creator>Sánchez, J. L.</creator><creator>Estévez, J. I.</creator><creator>Sigut, J. F.</creator><creator>Moreno, L.</creator><general>Wiley Subscription Services, Inc., A Wiley Company</general><scope>BSCLL</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>7TB</scope><scope>FR3</scope><scope>KR7</scope></search><sort><creationdate>2002</creationdate><title>Procedures based on simulation and hardware for a computer architecture course</title><author>González, E. J. ; Alayón, S. ; Piñeiro, J. D. ; Sánchez, J. L. ; Estévez, J. I. ; Sigut, J. F. ; Moreno, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3282-46a8be2e3dd9b53926298fe11d74f51a6e44a7f01073c184537363991b08a6093</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Architecture</topic><topic>Computer simulation</topic><topic>Education</topic><topic>Hardware</topic><topic>Interconnection</topic><topic>Mathematical models</topic><topic>networks</topic><topic>Packages</topic><topic>procedures</topic><topic>Processors</topic><topic>simulation</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>González, E. J.</creatorcontrib><creatorcontrib>Alayón, S.</creatorcontrib><creatorcontrib>Piñeiro, J. D.</creatorcontrib><creatorcontrib>Sánchez, J. L.</creatorcontrib><creatorcontrib>Estévez, J. I.</creatorcontrib><creatorcontrib>Sigut, J. F.</creatorcontrib><creatorcontrib>Moreno, L.</creatorcontrib><collection>Istex</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><jtitle>Computer applications in engineering education</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>González, E. J.</au><au>Alayón, S.</au><au>Piñeiro, J. D.</au><au>Sánchez, J. L.</au><au>Estévez, J. I.</au><au>Sigut, J. F.</au><au>Moreno, L.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Procedures based on simulation and hardware for a computer architecture course</atitle><jtitle>Computer applications in engineering education</jtitle><addtitle>Comput. Appl. Eng. Educ</addtitle><date>2002</date><risdate>2002</risdate><volume>10</volume><issue>1</issue><spage>11</spage><epage>17</epage><pages>11-17</pages><issn>1061-3773</issn><eissn>1099-0542</eissn><abstract>In this study, a procedure planning for a Computer Architecture Course that tries to create a balance between simulation and laboratory procedures is presented. For this planning, we use hardware implementation for parts of this subject that require careful dedication because of its complexity: interconnection networks and parallel processing. On the other hand, we use simulation packages for the teaching of pipelined and vectorial processors. © 2002 Wiley Periodicals, Inc. Comput Appl Eng Educ 10: 11–17, 2002; Published online in Wiley InterScience (www.interscience.wiley.com.); DOI 10.1002/cae.10012</abstract><cop>New York</cop><pub>Wiley Subscription Services, Inc., A Wiley Company</pub><doi>10.1002/cae.10012</doi><tpages>7</tpages></addata></record> |
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| ispartof | Computer applications in engineering education, 2002, Vol.10 (1), p.11-17 |
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| language | eng |
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| source | Wiley Journals |
| subjects | Architecture Computer simulation Education Hardware Interconnection Mathematical models networks Packages procedures Processors simulation |
| title | Procedures based on simulation and hardware for a computer architecture course |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T03%3A36%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Procedures%20based%20on%20simulation%20and%20hardware%20for%20a%20computer%20architecture%20course&rft.jtitle=Computer%20applications%20in%20engineering%20education&rft.au=Gonz%C3%A1lez,%20E.%20J.&rft.date=2002&rft.volume=10&rft.issue=1&rft.spage=11&rft.epage=17&rft.pages=11-17&rft.issn=1061-3773&rft.eissn=1099-0542&rft_id=info:doi/10.1002/cae.10012&rft_dat=%3Cproquest_cross%3E753650667%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=27638634&rft_id=info:pmid/&rfr_iscdi=true |