Nondestructive, in-line characterization of device performance parameters of shallow junction processes

Deep submicron transistor source–drain structures require a challenging combination of ultrashallow depth and low series resistance. Because these factors affect off-state leakage, drive current, and threshold voltage, it is important to maintain tight control of junction depth and depth uniformity over the full wafer diameter. A method for nondestructive, small area, high throughput characterization of ultrashallow junctions, called Carrier Illumination™ (CI) has recently been developed. It offers the potential for in-line monitoring of critical parameters associated with shallow junction processes. The CI method measures the active doping depth of shallow implants such as source/drain extensions on product wafers. Recent results demonstrate the ability of CI measurements to indicate junction depth variation due to implant dose, energy, and annealing temperature and time. This article presents correlation of in-line CI junction depth measurements to end-of-the line electrical properties of n metal–oxide–semiconductor (MOS) and pMOS transistors and test structures. This indicates that it is possible to maintain process control of the effective channel length and threshold voltage at front-end process steps, well before electrical probing is possible.