The multicluster architecture: Reducing processor cycle time through partitioning

A multicluster architecture offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of the architecture are distributed across multiple clusters, and each cluster is assigned a subset of the architectural registers. The motivation for the multicluster architecture is to reduce the clock cycle time, relative to a single-cluster architecture with the same number of hardware resources, by reducing the size and complexity of components on critical timing paths. Resource partitioning, however, introduces instruction-execution overhead and may reduce the number of concurrently executing instructions. To counter these 2 negative by-products of partitioning, a static instruction scheduling algorithm is developed. This algorithm is described, and using trace-driven simulations of SPEC92 benchmarks, its effectiveness is evaluated. This evaluation indicates that for the configurations considered, the multicluster architecture may have significant performance advantages and warrants further investigation.