Principle of designing slope compensation in PFC Boost converter

Due to wide input fluctuation with line frequency of 50 Hz, power-factor-correction （PFC） Boost converters tend to exhibit fast-scale instability over time domain. The traditional remedy is to impose slope compensation so as to weaken or eliminate this instability. A theoretical principle on the implementation of slope compensation signal is still lacking. Empirical design will induce over compensation frequently, resulting in a large decrease of power factor. In order to tackle this issue, by constructing the discrete-time iterative map of the PFC Boost converter from the viewpoint of bifurcation control theory of nonlinear systems, consequently, the criterion of critical stability for the PFC circuit can be established. Based on this stability criterion, appropriate design of slope compensation can be achieved. Our work indicates that 3 main circuit parameters （i.e. switching cycle, output reference voltage and inductor） determine the effective amplitude design of the slope compensation signal. The results, validated by a large quantity of analytical and numerical studies, show that appropriate slope compensation can be effective in weakening （or controlling） fast-scale bifurcation while maintaining a rather high input power factor.