Optimization of the spacer layer thickness in AlInAs/InGaAs/InP MODFETs

The effects of spacer layer thickness variations on single atomic planar doped (APD) AlInAs/InGaAs modulation doped field effect transistors grown by solid source molecular beam epitaxy have been studied and characterized. The thickness of the AlInAs spacer layer was varied between 0 and 100Å. Room temperature Hall measurements found the mobility exhibited an exponential relationship ranging from 6500 to 10800 cm^sup 2^/Vs. The sheet charge varied linearly from 3.46 × 10^sup 12^ cm^sup -2^ to 2.24 × 10^sup 12^ cm^sup -2^. An optimum spacer layer thickness based on maximum channel conductance was found to be 40Å with a mobility of 9600 cm^sup 2^/Vs and a sheet charge of 3.0 × 10^sup 12^ cm^sup -2^. The loss of mobility due to remote ion scattering was examined. This loss was related to the distribution of the Si atoms in the atomic planar doped layer in order to obtain the standard deviation of the interface. This relationship will allow various growth parameters, such as substrate temperature, growth rate, and V/III ratio to be altered to determine the optimum conditions independent of the growth chamber used to create the structures. [PUBLICATION ABSTRACT]