The M-Machine multicomputer

The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints of modern semiconductor technology and the demands of programming systems. The M-Machine computing nodes are connected with a 3-D mesh network; each node is a multithreaded processor incorporating 9 function units, on-chip cache, and local memory. The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently to the user with a combination of hardware and software mechanisms. The architecture of the M-Machine is presented, and it is described how its mechanisms attempt to maximize both single thread performance and overall system throughput, The architecture is complete and the MAP chip, which will serve as the M-Machine processing node, is currently being implemented.