Input-queued router architectures exploiting cell-based switching fabrics

Input queued and combined input/output-queued architectures have recently come to play a major role in the design of high-performance switches and routers for packet networks. These architectures must be controlled by a packet scheduling algorithm, which solves contentions in the transfer of data units to switch outputs. Several scheduling algorithms were proposed in the literature for switches operating on fixed-size data units. In this paper we consider the case of packet switches, i.e., devices operating on variable-size data units at their interfaces, but internally operating on fixed-size data units, and we propose novel extensions of known scheduling algorithms for input queued and combined input/output-queued architectures. We show by simulation that, in the case of packet switches, input queued and combined input/output-queued architectures can provide performance advantages over output-queued architectures.