Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

We compare four circuit methods for single event (SE) mitigation: single string with radiation-hardened flip flops, delay-guarded logic, dual-rail logic, and triple modular redundancy (TMR). Test results of the circuit methods at 180 nm are presented. We then describe a novel reprogrammable FPGA arc...

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Veröffentlicht in:IEEE transactions on nuclear science 2009-02, Vol.56 (1), p.214-219
Hauptverfasser: Shuler, R.L., Bhuva, B.L., O'Neill, P.M., Gambles, J.W., Rezgui, S.
Format: Artikel
Sprache:eng
Schlagworte:
Architecture
Circuit testing
Circuits
Complementary metal-oxide-semiconductor (CMOS)
Cost effectiveness
Costs
digital circuits
field programmable gate array (FPGA)
Field programmable gate arrays
Hardware
Logic
Logic circuits
Manufacturing
Modular
Protection
radiation-hardening
Reconfigurable logic
Redundancy
sequential circuits
single event
Single event upset
Strings
Tolerances
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Beschreibung
Zusammenfassung:We compare four circuit methods for single event (SE) mitigation: single string with radiation-hardened flip flops, delay-guarded logic, dual-rail logic, and triple modular redundancy (TMR). Test results of the circuit methods at 180 nm are presented. We then describe a novel reprogrammable FPGA architecture which can be configured based on SE mitigation and performance needs, and we evaluate the candidate SE mitigation methods as to suitability for such architecture.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2008.2010320