Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization

Leakage current minimization is an important topic for event driven applications that spend most of their times in standby mode. Power gating technique is one of the most effective ways to reduce the standby leakage current. However, when power gating technique is applied to a functional unit, there exists a delay-power tradeoff, which can be characterized with the widths of sleep transistors. In this paper, we point out that: under the same target clock period, there are many feasible clock skew schedules; since different clock skew schedules impose different timing constraints to functional units, different clock skew schedules may lead to different standby leakage currents. Based on that observation, we present an MLP (mixed integer linear programming) approach to formally formulate the problem of simultaneous application of optimal clock skew scheduling and power-gated module selection (i.e., sleep transistor width selection) in high-level synthesis stage. Experimental data show that: compared with the existing design flow, our standby leakage current reduction achieves 29.3%.