An offline placement algorithm for reconfigurable computing systems

In order to estimate a program's execution time on reconfigurable devices and perform hardware-software code partition, an offline placement algorithm is proposed to map all the basic blocks onto reconfigurable devices, so that logical synthesis or other methods can be used to estimate the generated circuits' execution time. Also an IP-Core based code transformation method is used to convert the basic blocks' data flow graphs into task graphs which are the inputs of the placement algorithm. Experiments show that although the placement result is locally optimal and that the generated circuits are 6. 891% slower and 4. 016% larger compared with the placer of Xilinx ISE toolset, the proposed algorithm can execute 105 times faster, which will greatly reduce the compiler's total execution time.