vMask(R) Usage in Semiconductor Foundry Manufacturing

Time and cost of development are key factors for the success of advanced devices. Device development requires multiple iterations of carefully designed implant splits to optimize device performance and yield. Conventional whole wafer implant splits are both time consuming and costly, due in part to the need to gain adequate statistics with the relatively high wafer to wafer variability of early stage development devices. VMASK, which provides multiple implant conditions on a single wafer, can be applied for a variety of corner splits, such as well, halo, and LDD implants to achieve target device performance and optimize process flow. By reducing the impact of variability from other process steps and the direct reduction in the number of device wafers required by a factor of four, a significant reduction in both wafer cost and cycle time can be achieved. In this paper, the benefits of VMASK were discussed and evaluated in a high volume production foundry fab and applied in the process development.