A Study of Implanted BF2 as a Function of Wafer Temperature During Implant

The temperature effect for buried channel PMOS transistor characteristics was investigated. Generally, only dose, energy and implant angle have been considered as the major parameters for process matching between different high current implanters in transistor manufacturing. However, as the device is scaled down to sub-100 nm size, additional parameters such as instantaneous dose rate and wafer temperature have become increasingly important for controlling the dopant profile by changing the annealing behavior of defects. The dose rate difference between ribbon and spot beam implanter was investigated through simulation and the wafer temperature difference was directly measured with special temperature measurement device. The peak height of both the boron and fluorine SIMS profiles corresponding to the location of the amorphous/crystalline (a/c) interface increased proportionally with increasing wafer temperature and to a lesser degree with increasing instantaneous dose rate. By increasing the wafer temperature, the threshold voltage (VT) decreased dramatically while the active area sheet resistance remained constant. This higher secondary peak height resulted in enhanced lateral diffusion, shorter effective channel length, and therefore a lower threshold voltage (VT).