Ultra-Shallow Junction Formation-Physics and Advanced Technology

In this paper, the advanced technology in the ultra-shallow junction formation and its physical understanding for sub-nano CMOS devices are presented. After quickly presenting the device issues for the next generation of CMOS devices, we shall focus on the formation of highly activated Ultra-Shallow Source Drain extension. In fact, the formation of ultra-shallow junctions (USJ) for future integrated circuit technologies requires achieving high activation levels and abrupt profiles. To achieve the challenging targets set out in the semiconductor roadmap, it is crucial to reach a much better understanding of the basic physical processes taking place during USJ processing. Subsequently, we review current understanding of dopant-defect interactions during thermal processing of device structures-interactions which are at the heart of the dopant diffusion and activation anomalies seen in USJ leading to device performance degradation. Based on the physical understanding, we shall review and discuss some promising methods, such as co-implants (C, F, N), cluster/molecular implants and defect engineering as well as alternative thermal processes, for further downscaling of source-drain resistance and junction depth. Emphasize on the impact on both PMOS and NMOS device performance will be presented. Finally, we will demonstrate that TCAD (Technology Computer Aided Design) can be successfully used for optimizing the new junction architecture to meet the nano-CMOS device performance requirements.