Low-Threshold-Voltage TaN/LaTiO n-MOSFETs With Small EOT

In this letter, we report a low threshold voltage ( V t ) of 0.12 V in self-aligned gate-first TaN/LaTiO n-MOSFETs, at an equivalent oxide thickness of only 0.63 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Sb that reduced the high-kappa dielectric interfacial...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE electron device letters 2009-09, Vol.30 (9), p.999-1001
Hauptverfasser:	Lin, S.H., Yeh, F.S., Cheng, C.H., Chin, A., Chen, W.B.
Format:	Artikel
Sprache:	eng
Schlagworte:	Annealing Antimony Applied sciences Bonding Capacitance Channel bank filters Dielectrics Diffusion Electronics Equivalence Exact sciences and technology Hafnium oxide Interface reactions LaTiO Lead compounds Leakage current low V_{t} MOSFET circuits Nickel Oxides Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon dioxide solid-phase diffusion (SPD) Threshold voltage Transistors
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	In this letter, we report a low threshold voltage ( V t ) of 0.12 V in self-aligned gate-first TaN/LaTiO n-MOSFETs, at an equivalent oxide thickness of only 0.63 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Sb that reduced the high-kappa dielectric interfacial reactions.
ISSN:	0741-3106 1558-0563
DOI:	10.1109/LED.2009.2027723