Memory window widening of Pt/SrBi2Ta2O9/HfO2/Si ferroelectric-gate field-effect transistors by nitriding Si

The optimum temperature of rapid thermal nitridation (RTN) of Si substrates was investigated for minimizing an equivalent oxide thickness (EOT) of an interfacial layer (IL) which was grown between HfO2 and Si of Pt/SrBi2Ta2O9(SBT)/HfO2/Si ferroelectric-gate field-effect transistors (FeFETs) during a post-annealing process. The RTN was performed in NH3 gas at various temperatures ranging from 800 deg C to 1190 deg C. As the RTN temperature was raised from 800 deg C to 1080 deg C, memory windows of drain current-gate voltage curves became wider. Large memory windows were obtained at the range from 1020 deg C to 1130 deg C. The maximum was 1.36 V obtained at 1080 deg C. It was 10% larger than the typical values of Pt/SBT/HfO2/Si FeFETs without the RTN. At higher RTN temperatures than 1080 deg C, the memory windows tended to decrease. At 800 deg C and 1190 deg C, all layer boundaries among SBT-HfO2-IL-Si seemed unclear in scanning transmission electron microscopic views probably due to material diffusions. The optimum RTN temperature for minimizing the EOT of the IL and maximizing the memory window of the Pt/SBT/HfO2/SiNx/Si FeFET was 1080 deg C. The FeFET using the Si processed by the RTN at 1080 deg C also showed good retentions without significant degradations over two days.