A Heavy-Ion Tolerant Clock and Data Recovery Circuit for Satellite Embedded High-Speed Data Links

A clock and data recovery (CDR) circuit dedicated to satellite embedded high-speed data links is implemented in a 0.13 mum CMOS technology. Its radiation hardening is obtained thanks to an innovative architecture based on an injection-locked oscillator (ILO) associated with a phase-alignment circuit...

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Veröffentlicht in:	IEEE transactions on nuclear science 2007-12, Vol.54 (6), p.2080-2085
Hauptverfasser:	Lapuyade, H., Mazouffre, O., Goumballa, B., Pignol, M., Malou, F., Neveu, C., Pouget, V., Deval, Y., Begueret, J.B.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit testing Circuits Clock and data recovery (CDR) Clocks CMOS CMOS technology Data links Data recovery Flip-flops Frequency synchronization heavy-ion testing High speed high-speed data links Injection-locked oscillators injection-locked oscillators (ILO) laser testing Oscillators Phase locked loops Radiation hardening radiation hardening by design Satellites single-event transients (SET) Voltage-controlled oscillators
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Beschreibung
Zusammenfassung:	A clock and data recovery (CDR) circuit dedicated to satellite embedded high-speed data links is implemented in a 0.13 mum CMOS technology. Its radiation hardening is obtained thanks to an innovative architecture based on an injection-locked oscillator (ILO) associated with a phase-alignment circuit. Its low single-event transient (SET) sensitivity is shown thanks to heavy-ion and laser testing.
ISSN:	0018-9499 1558-1578
DOI:	10.1109/TNS.2007.910866