A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra-Prediction
In this paper, we present a fast mode decision algorithm and design its VLSI architecture for H.264 intra-prediction. A regular spatial domain filtering technique is proposed to compute the dominant edge strength (DES) to reduce the possible predictive modes. Experimental results revealed that the p...
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Veröffentlicht in: | IEEE transactions on circuits and systems for video technology 2007-10, Vol.17 (10), p.1414-1422 |
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description | In this paper, we present a fast mode decision algorithm and design its VLSI architecture for H.264 intra-prediction. A regular spatial domain filtering technique is proposed to compute the dominant edge strength (DES) to reduce the possible predictive modes. Experimental results revealed that the proposed fast intra-algorithm reduces 40% computation with slight peak signal-to-noise ratio (PSNR) degradation. The designed DES VLSI engine comprises a zigzag converter, a DES finite-state machine (FSM), and a DES core. The former two units handle memory allocation and control flow while the last performs pseudoblock computation, edge filtering, and dominant edge strength extraction. With semicustom design fabricated by 0.18 mum CMOS single-poly-six-metal technology, the realized die size is roughly 0.15 times 0.15 mm 2 and can be operated at 66 MHz. |
doi_str_mv | 10.1109/TCSVT.2007.903786 |
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A regular spatial domain filtering technique is proposed to compute the dominant edge strength (DES) to reduce the possible predictive modes. Experimental results revealed that the proposed fast intra-algorithm reduces 40% computation with slight peak signal-to-noise ratio (PSNR) degradation. The designed DES VLSI engine comprises a zigzag converter, a DES finite-state machine (FSM), and a DES core. The former two units handle memory allocation and control flow while the last performs pseudoblock computation, edge filtering, and dominant edge strength extraction. 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Testing ; Detection, estimation, filtering, equalization, prediction ; dominant edge extraction ; Electronics ; Exact sciences and technology ; Filtering ; Filtration ; H264 ; IEC standards ; Image processing ; Information, signal and communications theory ; Integrated circuits ; intra-mode decision ; intra-prediction ; PSNR ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal and communications theory ; Signal processing ; Signal, noise ; Strength ; Telecommunications and information theory ; Very large scale integration ; Video coding</subject><ispartof>IEEE transactions on circuits and systems for video technology, 2007-10, Vol.17 (10), p.1414-1422</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2007</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c451t-875d52f6e46c4fcb5c89c04597a8c2f300ea2aa7d224d6fd6c13cec42a5f0fe23</citedby><cites>FETCH-LOGICAL-c451t-875d52f6e46c4fcb5c89c04597a8c2f300ea2aa7d224d6fd6c13cec42a5f0fe23</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4335637$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4335637$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=19133300$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>WANG, Jia-Ching</creatorcontrib><creatorcontrib>WANG, Jhing-Fa</creatorcontrib><creatorcontrib>YANG, Jar-Ferr</creatorcontrib><creatorcontrib>CHEN, Jang-Ting</creatorcontrib><title>A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra-Prediction</title><title>IEEE transactions on circuits and systems for video technology</title><addtitle>TCSVT</addtitle><description>In this paper, we present a fast mode decision algorithm and design its VLSI architecture for H.264 intra-prediction. A regular spatial domain filtering technique is proposed to compute the dominant edge strength (DES) to reduce the possible predictive modes. Experimental results revealed that the proposed fast intra-algorithm reduces 40% computation with slight peak signal-to-noise ratio (PSNR) degradation. The designed DES VLSI engine comprises a zigzag converter, a DES finite-state machine (FSM), and a DES core. The former two units handle memory allocation and control flow while the last performs pseudoblock computation, edge filtering, and dominant edge strength extraction. With semicustom design fabricated by 0.18 mum CMOS single-poly-six-metal technology, the realized die size is roughly 0.15 times 0.15 mm 2 and can be operated at 66 MHz.</description><subject>Advanced video coding (AVC)</subject><subject>Algorithm design and analysis</subject><subject>Algorithms</subject><subject>Applied sciences</subject><subject>Automatic voltage control</subject><subject>CMOS technology</subject><subject>Computation</subject><subject>Computer architecture</subject><subject>Degradation</subject><subject>Design engineering</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Detection, estimation, filtering, equalization, prediction</subject><subject>dominant edge extraction</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Filtering</subject><subject>Filtration</subject><subject>H264</subject><subject>IEC standards</subject><subject>Image processing</subject><subject>Information, signal and communications theory</subject><subject>Integrated circuits</subject><subject>intra-mode decision</subject><subject>intra-prediction</subject><subject>PSNR</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal and communications theory</subject><subject>Signal processing</subject><subject>Signal, noise</subject><subject>Strength</subject><subject>Telecommunications and information theory</subject><subject>Very large scale integration</subject><subject>Video coding</subject><issn>1051-8215</issn><issn>1558-2205</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kUtLAzEUhQdRsFZ_gLgJgrqaNu_HslRrCxWV1m5DzCR1ynRGk-nCf29qi4ILV_fC_c6Bc0-WnSPYQwiq_nw4W8x7GELRU5AIyQ-yDmJM5hhDdph2yFAuMWLH2UmMKwgRlVR0sucBGJnYgoemcODW2TKWTQ0G1bIJZfu2BqYuwKSNYDGdTdI9lssa-CaAcQ9z2h8shmBSt8HkT8EVpW2T-DQ78qaK7mw_u9nL6G4-HOfTx_vJcDDNLWWozaVgBcOeO8ot9faVWakspEwJIy32BEJnsDGiwJgW3BfcImKdpdgwD73DpJvd7HzfQ_OxcbHV6zJaV1Wmds0maikVEYJSmMjrf0lCqVKcswRe_gFXzSbUKYVWCGNEEeIJQjvIhibG4Lx-D-XahE-NoN52ob-70Nsu9K6LpLnaG5toTeWDqdOnf4UKEZISJ-5ix5XOuZ8zJYRxIsgXLqCPKw</recordid><startdate>20071001</startdate><enddate>20071001</enddate><creator>WANG, Jia-Ching</creator><creator>WANG, Jhing-Fa</creator><creator>YANG, Jar-Ferr</creator><creator>CHEN, Jang-Ting</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Technologies. Operation analysis. Testing</topic><topic>Detection, estimation, filtering, equalization, prediction</topic><topic>dominant edge extraction</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Filtering</topic><topic>Filtration</topic><topic>H264</topic><topic>IEC standards</topic><topic>Image processing</topic><topic>Information, signal and communications theory</topic><topic>Integrated circuits</topic><topic>intra-mode decision</topic><topic>intra-prediction</topic><topic>PSNR</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. 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A regular spatial domain filtering technique is proposed to compute the dominant edge strength (DES) to reduce the possible predictive modes. Experimental results revealed that the proposed fast intra-algorithm reduces 40% computation with slight peak signal-to-noise ratio (PSNR) degradation. The designed DES VLSI engine comprises a zigzag converter, a DES finite-state machine (FSM), and a DES core. The former two units handle memory allocation and control flow while the last performs pseudoblock computation, edge filtering, and dominant edge strength extraction. With semicustom design fabricated by 0.18 mum CMOS single-poly-six-metal technology, the realized die size is roughly 0.15 times 0.15 mm 2 and can be operated at 66 MHz.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TCSVT.2007.903786</doi><tpages>9</tpages></addata></record> |
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subjects | Advanced video coding (AVC) Algorithm design and analysis Algorithms Applied sciences Automatic voltage control CMOS technology Computation Computer architecture Degradation Design engineering Design. Technologies. Operation analysis. Testing Detection, estimation, filtering, equalization, prediction dominant edge extraction Electronics Exact sciences and technology Filtering Filtration H264 IEC standards Image processing Information, signal and communications theory Integrated circuits intra-mode decision intra-prediction PSNR Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal and communications theory Signal processing Signal, noise Strength Telecommunications and information theory Very large scale integration Video coding |
title | A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra-Prediction |
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