Analysis and Design of RF CMOS Attenuators

Analysis and Design of RF CMOS Attenuators

Attenuators are analyzed for their minimum Insertion Loss (IL), maximum attenuation and source-load matching performance. These results are used to make trade-offs in the design of a CMOS attenuator with wide dynamic range, designed and fabricated in a 0.13 mum CMOS process. The design employs two n...

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Veröffentlicht in:IEEE journal of solid-state circuits 2008-10, Vol.43 (10), p.2269-2283
Hauptverfasser: Dogan, H., Meyer, R.G., Niknejad, A.M.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Attenuation
attenuation control loop
Attenuator
attenuator analysis
Attenuators
CMOS
CMOS attenuator
CMOS process
Design engineering
Design. Technologies. Operation analysis. Testing
Dynamic range
Electronics
Exact sciences and technology
Frequency bands
highly linear attenuator
Insertion loss
Integrated circuits
Linearity
Noise levels
parasitic effects on attenuators
Performance analysis
Performance loss
Process design
Radio frequency
RF attenuator
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Tradeoffs
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Beschreibung
Zusammenfassung:Attenuators are analyzed for their minimum Insertion Loss (IL), maximum attenuation and source-load matching performance. These results are used to make trade-offs in the design of a CMOS attenuator with wide dynamic range, designed and fabricated in a 0.13 mum CMOS process. The design employs two non-identical cascaded T-stages that are activated consecutively to improve linearity. The design operates in the frequency band of DC-2.5 GHz with 0.9-3.5 dB insertion loss and 42 dB maximum attenuation in the entire frequency range. Worst case S11 is - 8.2 dB across the frequency band. The design achieves an IIP3 of + 20 dBm at mid-attenuation.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2008.2004325