Analog inner product operations for image compression in 0.35-mum CMOS

We propose a new model for analyzing the sensitivity of inner products to CMOS analog hardware implementation. It is derived from Spice simulations of the circuits to be implemented, and it is required for the design of analog image compression systems based on vector quantization at the focal plane of CMOS imaging sensors. The model is shown to be equivalent to a simpler and previously introduced theoretical model, if the errors caused by the fabrication process are around 6%. For 1.5% errors, the results differ from the theoretical predictions made by the previous model. Image compression results obtained with a prototype circuit fabricated in a 0.35-mum CMOS process are presented, and show close agreement with both theoretical and simulation predictions.