Small size low noise amplifier with suppressed noise from gate resistance

In this article, design and characterization results of a fully integrated 5.8 GHz low noise amplifier (LNA) using 0.13‐μm CMOS technology are presented. Commonly adopted inductive source degeneration for input impedance matching is eliminated to achieve smaller chip area while providing reasonable 50‐Ω matching. Also by adding a capacitor between the gate and the source of the input transistor, a noise source from the gate resistance is partly suppressed. The layout of the designed LNA occupies total area of 0.68 mm2 and the results show forward power gain (S21) of 12.7 dB and noise figure of 3.9 dB while consuming 6.85 mW from 1.2‐V DC supply. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2300–2304, 2008; Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.23702