Low damage ashing and etching processes for ion implanted resist and Si3N4 removal by ICP and RIE methods

This paper presents a low damage, ion implantation mask removal process where the ion implantation mask, consisting of photoresist and Si3N4 deposited by room temperature ICP-CVD (inductively coupled plasma chemical vapour deposition), has been successfully removed through combining ICP (inductively coupled plasma) O2 plasma ashing and SF6/O2 reactive ion etching (RIE) of the Si3N4. The process leaves a clean, smooth post-etching surface with rms roughness of less than 1nm, on a device quality, high-κ GaxGdyOz (GGO) oxide layer for the fabrication of III–V metal-oxide-semiconductor field-effect-transistors (MOSFETs). Equally importantly, no etch induced damage occurs in the underlying high mobility III–V semiconductor layers. The post-etched GGO surface roughness and electrical transport properties of the underlying device layer structures were characterised by atomic force microscopy (AFM) and sonogage, respectively.