A Universal Shifter with Packed Data Formats

A Universal Shifter with Packed Data Formats

In this letter, we propose a universal shifter architecture which executes parallel vector shift operations as well as data reorganizing operations concerning packed data formats. The universal shifter is beneficial in cost-effectively implementing microprocessors' SIMD ISA extensions. It reduc...

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Veröffentlicht in:International journal of electronics and communications 2003, Vol.57 (6), p.420-422
Hauptverfasser: Jeong, Woo-Kyeong, Lee, Yong-Surk
Format: Artikel
Sprache:eng
Schlagworte:
Barrel shifter
Crossbar network
Packed data
SIMD
Universal shifter
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container_issue 6
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container_title International journal of electronics and communications
container_volume 57
creator Jeong, Woo-Kyeong
Lee, Yong-Surk
description In this letter, we propose a universal shifter architecture which executes parallel vector shift operations as well as data reorganizing operations concerning packed data formats. The universal shifter is beneficial in cost-effectively implementing microprocessors' SIMD ISA extensions. It reduces the overall occupied area by 56% and delay time by 6% compared to the conventional implementations which have duplicated operational units.
doi_str_mv 10.1078/1434-8411-54100195
format Article
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ispartof International journal of electronics and communications, 2003, Vol.57 (6), p.420-422
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language eng
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source Elsevier ScienceDirect Journals; ProQuest Central UK/Ireland
subjects Barrel shifter
Crossbar network
Packed data
SIMD
Universal shifter
title A Universal Shifter with Packed Data Formats
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