Functional tests of a 0.6 mum CMOS MLP analog neural network for fast on-board signal processing

The feedforward multi-layer perceptron (MLP) type neural network (NN) presented in this paper has been developed for on-board applications of high-speed signal processing. It is fully analog in order to avoid analog-digital conversions and to limit chip size and power consumption. It is constituted by a single input, ten neurons in the hidden layer and a single output. The MLP-NN has been implemented in a 84 pins (0.6 mum CMOS ASIC) and has a power consumption of 600 mW. The NN layout size is 1.8 mm X 0.7 mm. This paper reminds the design and the simulations of each implemented cell and details the different experimental tests achieved.