PowerViP: Soc power estimation framework at transaction level

PowerViP: Soc power estimation framework at transaction level

In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different mode...

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Bibliographische Detailangaben
Hauptverfasser: Lee, Ikhwan, Kim, Hyunsuk, Yang, Peng, Yoo, Sungjoo, Chung, Eui-Young, Choi, Kyu-Myung, Kong, Jeong-Taek, Eo, Soo-Kwan
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Hardware
Hardware > Hardware validation
Hardware > Hardware validation > Functional verification > Simulation and emulation
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Beschreibung
Zusammenfassung:In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design.
DOI:10.1145/1118299.1118431