Uniformity, Linearity, and Symmetry Enhancement in TiOx/MoS2-xOx Based Analog RRAM via S-Vacancy Confined Nanofilament

Due to the stochastic formation of conductive filaments (CFs), analog resistive random-access memory (RRAM) struggles to simultaneously achieve low variability, high linearity, and symmetry in conductance tuning, thus complicating on-chip training and limiting versatility of RRAM based computing-in-memory (CIM) chips. In this study, we present a simple and effective approach using monolayer (ML) MoS2 as interlayer to control the CFs formation in TiOx switching layer. The limited S-vacancies (Sv) in MoS2-xOx interlayer can further confine the position, size, and quantity of CFs, resulting in a highly uniform and symmetrical switching behavior. The set and reset voltages (Vset and Vreset) in TiOx/MoS2-xOx based RRAM are symmetric, with cycle-to-cycle variations of 1.28% and 1.7%, respectively. Moreover, high conductance tuning linearity and 64-level switching capabilities are achieved, which facilitate high accuracy (93.02%) on-chip training. This method mitigates the device nonidealities of analog RRAM through Sv confined CFs, accelerating the development of RRAM based CIM chips.Due to the stochastic formation of conductive filaments (CFs), analog resistive random-access memory (RRAM) struggles to simultaneously achieve low variability, high linearity, and symmetry in conductance tuning, thus complicating on-chip training and limiting versatility of RRAM based computing-in-memory (CIM) chips. In this study, we present a simple and effective approach using monolayer (ML) MoS2 as interlayer to control the CFs formation in TiOx switching layer. The limited S-vacancies (Sv) in MoS2-xOx interlayer can further confine the position, size, and quantity of CFs, resulting in a highly uniform and symmetrical switching behavior. The set and reset voltages (Vset and Vreset) in TiOx/MoS2-xOx based RRAM are symmetric, with cycle-to-cycle variations of 1.28% and 1.7%, respectively. Moreover, high conductance tuning linearity and 64-level switching capabilities are achieved, which facilitate high accuracy (93.02%) on-chip training. This method mitigates the device nonidealities of analog RRAM through Sv confined CFs, accelerating the development of RRAM based CIM chips.