Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow

Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow

In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potenti...

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Hauptverfasser: Van Renterghem, K, Demuytere, P, Verhulst, D, Vandewege, J, Qiu, Xing-Zhi
Format: Tagungsbericht
Sprache:eng
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Zusammenfassung:In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potential bottlenecks.
DOI:10.1145/383251.383252