Conditional pre-charge techniques for power-efficient dual-edge clocking
A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower Energy-Delay Product for 50% data activity, as compared to the previously published dual edge-triggered...
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| creator | Nedovic, Nikola Aleksic, Marko Oklobdzija, Vojin G. |
| description | A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower Energy-Delay Product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18um process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications. |
| doi_str_mv | 10.1145/566408.566424 |
| format | Conference Proceeding |
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| identifier | ISBN: 1581134754 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Hardware -- Integrated circuits -- Logic circuits -- Sequential circuits |
| title | Conditional pre-charge techniques for power-efficient dual-edge clocking |
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